![](http://datasheet.mmic.net.cn/330000/MBM29LV200B_datasheet_16439156/MBM29LV200B_21.png)
21
MBM29LV200T/MBM29LV200B
Notes:
1. These status flags apply when outputs are read from a sector that has been erase-suspended.
2. These status flags apply when outputs are read from the byte address of the non-erase suspended
sector.
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode. (DQ
2
toggles
while DQ
6
does not.) See also Table 8 and Figure 17.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the devices are in the
erase mode, DQ
2
toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29LV200T/200B provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or completed. If the output is low, the devices are busy with
either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase
operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands.
If the MBM29LV200T/200B are placed in an Erase Suspend mode, the RY/BY output will be high. Also, since
this is an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV200T/200B devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to Figures 13 and 14 for the timing diagram.
Data Protection
The MBM29LV200T/200B are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
toggles
Erase Suspend Program
DQ
7
(Note 2)
toggles
1 (Note 2)