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參數(shù)資料
| 型號： | MBM29LV320BE10PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | #10/12 CONT.SBS50 LOW DET. |
| 中文描述： | 2M X 16 FLASH 3V PROM, 100 ns, PBGA63 |
| 封裝： | PLASTIC, FBGA-63 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大小： | 877K |
| 代理商： | MBM29LV320BE10PBT |
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MBM29LV320TE/BE
80/90/10
25
9.
Extended Sector Group Protection
In addition to normal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables to protect sector group by forcing V
ID
on RESET pin and write a command
sequence. Unlike conventional procedure, it is not necessary to force V
ID
and control timing for control pins. The
only RESET pin requires V
ID
for sector group protection in this mode. The extended sector group protection
requires V
ID
on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)
into the command register. Then, the sector group addresses pins (A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
)
and (A
6
, A
1
, A
0
)
=
(0, 1, 0) should be set to the sector group to be protected (recommend to set V
IL
for the other
addresses pins) , and write extended sector group protection command (60h) . A sector group is typically
protected in 250
μ
s. To verify programming of the protection circuitry, the sector group addresses pins (A
20
, A
19
,
A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
) and (A
6
, A
1
, A
0
)
=
(0, 1, 0) should be set and write a command (40h) . Following
the command write, a logical “1” at device output DQ
0
will produce for protected sector in the read operation. If
the output is logical “0”, please repeat to write extended sector group protection command (60h) again. To
terminate the operation, it is necessary to set RESET pin to V
IH
. (See “16. Extended Sector Group Protection
Timing Diagram” in
I
TIMING DIAGRAM and “7. Extended Sector Group Protection Algorithm” in
I
FLOW
CHART.)
10. RESET
Hardware Reset
The device may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse requirement and has to
be kept low (V
IL
) for at least “t
RP
” in order to properly reset the internal state machine. Any operation in the process
of being executed will be terminated and the internal state machine will be reset to the read mode “t
READY
” after
the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional
“t
RH
” before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the
duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program
or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal
should be ignored during the RESET pulse. See “10. RESET, RY/BY Timing Diagram” in
I
TIMING DIAGRAM
for the timing diagram. See “8. Temporary Sector Group Unprotection” for additional functionality.
11. Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
ID
.
This function is one of two provided by the WP/ACC pin.
If the system asserts V
IL
on the WP/ACC pin, the device disables program and erase functions in the two
“outermost” 8 K byte boot sectors independently of whether those sectors are protected or unprotected using
the method described in “Sector Protection/Unprotection”. The two outermost 8 K byte boot sectors are the two
sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the
highest addresses in a top-boot-congfigured device.
(MBM29LV320TE : SA69 and SA70, MBM29LV320BE : SA0 and SA1)
If the system asserts V
IH
on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in “Sector
protection/unprotection”.
12. Accelerated Program Operation
The device offers accelerated program operation which enables the programming in high speed. If the system
asserts V
ACC
to the WP/ACC pin, the device automatically enters the acceleration mode and the time required
for program operation will reduce to about 60
%
. This function is primarily intended to allow high speed program,
so caution is needed as the sector group will temporarily be unprotected.
The system would use a fast program command sequence when programming during acceleration mode. Set
command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used
for programming and detection of completion during acceleration mode.
Removing V
ACC
from the WP/ACC pin returns the device to normal operation. Do not remove V
ACC
from WP/
ACC pin while programming. See “17. Accelerated Program Timing Diagram” in
I
TIMING DIAGRAM.
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