參數(shù)資料
型號: MBM29LV320BE80TR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 32 M (4 M X 8/2 M X 16) BIT
中文描述: 2M X 16 FLASH 3V PROM, 80 ns, PDSO48
封裝: PLASTIC, REVERSE, TSOP1-48
文件頁數(shù): 23/64頁
文件大?。?/td> 877K
代理商: MBM29LV320BE80TR
MBM29LV320TE/BE
80/90/10
23
I
FUNCTIONAL DESCRIPTION
1.
Read Mode
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the
power control and should be used for a device selection. OE is the output control and should be used to gate
data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to delay from stable addresses to valid output data. The chip enable access
time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses
have been stable for at least t
ACC
-t
OE
time.) When reading out data without changing addresses after power-up,
it is necessary to input hardware reset or to change CE pin from “H” or “L”.
Standby Mode
2.
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the
other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
±
0.3 V.
Under this condition the current consumed is less than 5
μ
A Max During Embedded Algorithm operation, V
CC
active current (I
CC2
) is required even CE
=
“H”. The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
±
0.3 V (CE
=
“H” or “L”) . Under this condition the current consumed is less than 5
μ
A Max Once the RESET pin is taken
high, the device requires t
RH
as wake up time for outputs to be valid for read access.
In the standby mode the outputs are in the high impedance state, independently of the OE input.
Automatic Sleep Mode
3.
There is a function called automatic sleep mode to restrain power consumption during read-out of the device
data. This mode can be useful in the application such as a handy terminal which requires low power consumption.
To activate this mode, the device automatically switches themselves to low power mode when the device ad-
dresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode.
Under the mode, the current consumed is typically 1
μ
A (CMOS Level) .
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically, and the device read the data for changed addresses.
Output Disable
4.
With the OE input at a logic high level (V
IH
) , output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
5.
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the device outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON’T CARES except A
6
, A
1
, and A
0
(A
-1
) . (See “MBM29LV320TE/BE User Bus Operations
Tables (BYTE = V
IH
and BYTE = V
IL
)” in
I
DEVICE BUS OPERATIONS.)
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A
9
pin. The command sequence is
illustrated in “MBM29LV320TE/BE Command Definitions Table” (
I
DEVICE BUS OPERATIONS) (See “2.
Autoselect Command” in
I
COMAND DIFINITIONS) .
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