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參數(shù)資料
| 型號： | MBM29LV320TE80PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 32 M (4 M X 8/2 M X 16) BIT |
| 中文描述： | 2M X 16 FLASH 3V PROM, 80 ns, PBGA63 |
| 封裝： | PLASTIC, FBGA-63 |
| 文件頁數(shù)： | 27/64頁 |
| 文件大?。?/td> | 877K |
| 代理商： | MBM29LV320TE80PBT |
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MBM29LV320TE/BE
80/90/10
27
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the device requires that a valid address to the device be supplied by the
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-
gramming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“1. Embedded Program
TM
Algorithm” in
I
FLOW CHART illustrates the Embedded Program
TM
Algorithm using
typical command strings and bus operations.
Chip Erase
4.
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls
or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) , or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ
7
is “1” (See “12. Write Operation Status”.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time
×
All sectors
+
Chip Program Time (Preprogramming)
“2. Embedded Erase
TM
Algorithm” in
I
FLOW CHART illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
Sector Erase
5.
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data
=
30h) is latched on the rising edge of CE or WE which happens first.
After time-out of “t
TOW
” from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV320TE/BE
Command Definitions Table” in
I
DEVICE BUS OPERATIONS. This sequence is followed with writes of the
Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than “t
TOW
” otherwise that command will not be accepted and erasure will not start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of “t
TOW
” from the rising edge of
last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another
falling edge of CE or WE, whichever happens first occurs within the “t
TOW
” time-out window the timer is reset.
(Monitor DQ
3
to determine if the sector erase timer window is still open, see “16. DQ
3
”, Sector Erase Timer.)
Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the
read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt
the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (See “12.
Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 70) .
Sector erase does not require the user to program the device prior to erase. The device automatically program
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
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| MBM29LV320TE80TN | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE80TR | 32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320BE90TR | 32 M (4 M X 8/2 M X 16) BIT |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV320TE80TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE80TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE90PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32 M (4 M X 8/2 M X 16) BIT |
| MBM29LV320TE-90PFTN | 制造商:FUJITSU 功能描述: |
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