參數(shù)資料
型號(hào): MBM29LV320TE90TN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 32 M (4 M X 8/2 M X 16) BIT
中文描述: 2M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝: PLASTIC, TSOP1-48
文件頁(yè)數(shù): 34/64頁(yè)
文件大小: 877K
代理商: MBM29LV320TE90TN
MBM29LV320TE/BE
80/90/10
34
22. Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(Min) . If V
CC
<
V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when V
CC
is above V
LKO
(Min) .
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
23. Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (Typ) on OE, CE, or WE will not initiate a write cycle.
24. Logical Inhibit
Writing is inhibited by holding any one of OE
=
V
IL
, CE
=
V
IH
, or WE
=
V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
25. Power-Up Write Inhibit
Power-up of the device with WE
=
CE
=
V
IL
and OE
=
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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