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參數(shù)資料
| 型號： | MBM29LV400TC-90PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 4M (512K X 8/256K X 16) BIT |
| 中文描述： | 256K X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | PLASTIC, FBGA-48 |
| 文件頁數(shù)： | 18/58頁 |
| 文件大?。?/td> | 584K |
| 代理商： | MBM29LV400TC-90PBT |
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MBM29LV400TC
-70/-90/-12
/MBM29LV400BC
-70/-90/-12
18
SPA : Sector address to be protected. Set sector address (SA) and (A
6
, A
1
, A
0
) = (0, 1, 0).
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected
sector addresses.
*1
*2
*3
This command is valid while Fast Mode.
This command is valid while RESET= V
IH
.
This data "
00
H" is also acceptable.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
= 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Table 8 MBM29LV400TC/BC Extended Command Definitions
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Set to
Fast Mode
Word
3
555H
AAH
2AAH
55H
555H
20H
—
—
Byte
AAAH
555H
AAAH
Fast Program
*1
Word
2
XXXH
A0H
PA
PD
—
—
—
—
Byte
XXXH
Reset from
Fast Mode *1
Word
2
XXXH
90H
XXXH
F0H *3
—
—
—
—
Byte
XXXH
XXXH
Extended
Sector
Protect *2
Word
4
XXXH
60H
SPA
60H
SPA
40H
SPA
SD
Byte
相關PDF資料 |
PDF描述 |
|---|---|
| MBM29LV400TC-90PF | 4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-90PFTN | 4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-90PFTR | 4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-70PFTR | 4M (512K X 8/256K X 16) BIT |
| MBM29LV400BC | 4M (512K X 8/256K X 16) BIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV400TC-90PBT-S-ER | 制造商:FUJITSU 功能描述: |
| MBM29LV400TC-90PCV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-90PF | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-90PFTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:4M (512K X 8/256K X 16) BIT |
| MBM29LV400TC-90PFTN-S# | 制造商:FUJITSU 功能描述: |
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