- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377952 > MBM29LV652UE-12 (Fujitsu Limited) 64M (4M X 16) BIT PDF資料下載
參數(shù)資料
| 型號： | MBM29LV652UE-12 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 64M (4M X 16) BIT |
| 中文描述： | 64M號（4米× 16）位 |
| 文件頁數(shù)： | 27/58頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MBM29LV652UE-12 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
MBM29LV652UE-
90/12
27
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
Once the Embedded Algorithm operation is close to being completed, the MBM29LV652UE data pins (DQ
7
) may
change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving
status information on DQ
7
at one instant of time and then that byte’s valid data at the next instant of time.
Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 8.)
See Figure 9 for the Data Polling timing specifications and diagram.
DQ
6
Toggle Bit I
The MBM29LV652UE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1
μ
s and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400
s
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ
6
to toggle.
See Figure 10 for the Toggle Bit I timing specifications and diagram.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Table 2.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the devices have exceeded timing limits, the
DQ
5
bit will indicate a “1”. Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV652UE-90 | 64M (4M X 16) BIT |
| MBM29LV652UE90PBT | 64M (4M X 16) BIT |
| MBM29LV800BA | 8M (1M X 8/512K X 16) BIT |
| MBM29LV800BA-90 | LED Lamp; Bulb Size:T-1 3/4; LED Color:Amber; Luminous Intensity:2000ucd; Viewing Angle:20 ; Forward Current:20mA; Forward Voltage:2.1V; Operating Temperature Range:-25 C to +85 C; Color:Amber; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| MBM29LV800TA-12 | 122 x 32 pixel format, LED or EL Backlight available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV652UE-90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M X 16) BIT |
| MBM29LV652UE90PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M X 16) BIT |
| MBM29LV800BA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29LV800BA-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29LV800BA-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。