參數(shù)資料
型號： MBM29PDS322BE11PBT
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： 32M (2M x 16) BIT Page Dual Operation
中文描述： 2M X 16 FLASH 1.8V PROM, 115 ns, PBGA63
封裝： PLASTIC, FBGA-63
文件頁數(shù)： 19/66頁
文件大小： 694K
代理商： MBM29PDS322BE11PBT
MBM29PDS322TE/BE
10/11
19
I
FUNCTIONAL DESCRIPTION
Simultaneous Operation
The device has feature, which is capable of reading data from one bank of memory while a program or erase
operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional
features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be
selected by bank address (A
20
to A
15
) with zero latency.
The device has two banks which contain
Bank 1 (4 KW
×
eight sectors, 32 KW
×
seven sectors) and Bank 2 (32 KW
×
fifty-six sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 8 shows the possible
combinations for simultaneous operation. (Refer to Figure 12 Back-to-Back Read/Write Timing Diagram.)
Table 8 Simultaneous Operation
Bank 1 Status
Read mode
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
*: An erase operation may also be suspended to read from or program to a sector not being erased.
Read Mode
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the
power control and should be used for a device selection. OE is the output control and should be used as the
gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to delay from stable addresses to valid output data. The chip enable access
time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
access time (t
OE
) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses
have been stable for at least t
ACC
-t
OE
time.) When reading out data without changing addresses after power-up,
it is necessary to input hardware reset or to change CE pin from “H” or “L”.
Page Mode Read
The device is capable of fast Page mode read operation. This mode provides faster read access speed for
random locations within a page. The Page size of the device is 4 words, within the appropriate Page being
selected by the higher address bits A
20
to A
2
and the LSB bits A
1
and A
0
within that page. This is an asynchronous
operation with the microprocessor supplying the specific word location.
The random or initial page access is equal to t
ACC
and subsequent Page read access (as long as the locations
specified by the microprocessor fall within that Page) is equivalent to t
PACC
. Here again, CE selects the device
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A
20
to A
2
constant and changing A
1
and A
0
to select the specific
word, within that page. See Figure 5.4 for timing specifications.
Case
1
2
3
4
5
6
7
Bank 2 Status
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
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