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參數(shù)資料
| 型號(hào)： | MC-4516CB64ES |
| 廠商： | NEC Corp. |
| 英文描述： | 16 M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM |
| 中文描述： | 16米字，64位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊以便內(nèi)存 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | MC-4516CB64ES |
Data Sheet M13611EJ5V0DS00
6
MC-4516CB64ES, 4516CB64PS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1,
/CAS latency = 2
800
mA
1
t
RC
≥
t
RC (MIN.)
, I
O
= 0
mA
/CAS latency = 3
840
Precharge standby current
I
CC2
P
CKE
≤
V
IL (MAX.)
, t
CK
=
15
ns
8
mA
in power down mode
I
CC2
PS
CKE
≤
V
IL (MAX.)
, t
CK
=
∞
8
Precharge standby current
I
CC2
N
CKE
≥
V
IH (MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH (MIN.)
,
160
mA
in non power down mode
Input signals are changed one time during 30
ns.
I
CC2
NS
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
64
Active standby current in
I
CC3
P
CKE
≤
V
IL (MAX.)
, t
CK
=
15
ns
40
mA
power down mode
I
CC3
PS
CKE
≤
V
IL (MAX.)
, t
CK
=
∞
32
Active standby current in
I
CC3
N
CKE
≥
V
IH (MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH (MIN.)
,
240
mA
non power down mode
Input signals are changed one time during 30
ns.
I
CC3
NS
CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
160
Operating current
I
CC4
t
CK
≥
t
CK (MIN.)
, I
O
= 0
mA
/CAS latency = 2
680
mA
2
(Burst mode)
/CAS latency = 3
1,000
CBR (Auto) refresh current
I
CC5
t
RC
≥
t
RC (MIN.)
/CAS latency = 2
1,760
mA
3
/CAS latency = 3
1,760
Self refresh current
I
CC6
CKE
≤
0.2
V
16
mA
Input leakage current
I
I (L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
8
+
8
μ
A
Output leakage current
I
O (L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–
1.5
+
1.5
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
#
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