參數(shù)資料
型號: MC-454CB645
廠商: NEC Corp.
英文描述: 4M-Word By 64-BIT Dynamic RAM Module(4M×64位動態(tài)RAM模塊)
中文描述: 分詞,64位動態(tài)RAM模塊(4米× 64位動態(tài)內(nèi)存模塊)
文件頁數(shù): 1/16頁
文件大?。?/td> 132K
代理商: MC-454CB645
1998
MOS INTEGRATED CIRCUIT
MC-454CB645
4M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
DATA SHEET
The mark
shows major revised points.
Document No. M13296EJ3V0DS00 (3rd edition)
Date Published September 1998 NS CP (K)
Printed in Japan
The information in this document is subject to change without notice.
Description
The MC-454CB645 is a 4,194,304 words by 64 bits synchronous dynamic RAM module on which 4 pieces of 64M
SDRAM :
μ
PD4564163 (Rev. E) are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
4,194,304 words by 64 bits organization
Clock frequency and clock access time
Family
/CAS latency
Clock frequency
Clock access time
Power consumption (MAX.)
(MAX.)
(MAX.)
Active
Standby
MC-454CB645-A10B
CL = 3
100 MHz
7
ns
2,376
mW
7.2
mW
CL = 2
67 MHz
8
ns
1,584 mW
(CMOS level input )
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length : 1, 2, 4, 8 and full page
Programmable wrap sequence (sequential
/
interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10
±
10
% of series resistor
Single 3.3
V
±
0.3
V power supply
LVTTL compatible
4,096 refresh cycles / 64
ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27
mm)
Unbuffered type
Serial PD
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