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參數(shù)資料
| 型號： | MC-9400A |
| 廠商： | NEC Corp. |
| 英文描述： | 320 (240)-BIT AC- PDP DRIVER MODULE |
| 中文描述： | 320（240）位交流等離子體平板顯示驅(qū)動模塊 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 82K |
| 代理商： | MC-9400A |
5
MC-9400A
TRUTH TABLE
1. Shift register block
Input
Output
R,/L
/CLK
A
B
Shift register
H
↓
Output
Note1
Execution of right shift
H
X
Input
Output
Retain
L
↓
Output
Note2
Execution of left shift
L
X
Output
Input
Retain
Notes 1.
On a clock rise, the data S
57
, S
58
, S
59
, and S
60
are shifted to S
61
, S
62
, S
63
, and S
64
, and output from B
1
, B
2
, B
3
,
and B
4
, respectively.
2.
On a clock fall, the data S
5
, S
6
, S
7
, and S
8
are shifted to S
1
, S
2
, S
3
, and S
4
, and output from A
1
, A
2
, A
3
, and A
4
,
respectively.
Remark
X= H or L, H= High level, L= Low level
2. Latch block
LE
/CLK
Output state of latch block (/Ln)
↓
Latches the data of Sn and retains the output data
H
↓
Retains the latch data
L
X
Retains the latch data
Remark
X= H or L, H= High level, L= Low level
3. Driver block
/Ln
BLK
/PC
Driver output state
X
H
H
H (all driver outputs : H)
X
H
L
L (all driver outputs : L)
X
L
H
Outputs latch data (/Ln)
X
L
L
Outputs latch data (/Ln) with polarity inverted
Remark
X= H or L, H= High level, L= Low level
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