參數(shù)資料
型號(hào): MC100E256FN
廠商: ON SEMICONDUCTOR
元件分類: 鎖存器
英文描述: 100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 1/7頁
文件大?。?/td> 174K
代理商: MC100E256FN
Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 1
1
Publication Order Number:
MC100E256/D
MC100E256
5VECL 3-Bit 4:1 Mux-Latch
The MC100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls
are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic
HIGH on LEN latches the outputs. The Master Reset (MR) overrides
all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
950 ps Max. D to Output
850 ps Max. LEN to Output
Split Select
Differential Outputs
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 1 KV HBM, > 75 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 code V0 @ 1/8″,
Oxygen Index 28 to 34
Transistor Count = 280 devices
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC100E256FN
PLCC28
37 Units/Rail
MC100E256FNR2
PLCC28
500 Units/Reel
MARKING
DIAGRAM
A
= Assembly
Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
PLCC28
FN SUFFIX
CASE 776
MC100E256FN
AWLYYWW
1
28
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