參數(shù)資料
型號(hào): MC100EL51DTR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 0K
描述: IC FLIP FLOP CLK D DIFF 8-TSSOP
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 2,500
系列: 100EL
功能: 復(fù)位
類(lèi)型: D 型
輸出類(lèi)型: 差分
元件數(shù): 1
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 2.8GHz
延遲時(shí)間 - 傳輸: 475ps
觸發(fā)器類(lèi)型: 正邊沿
電源電壓: 4.2 V ~ 5.7 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 7
1
Publication Order Number:
MC10EL51/D
MC10EL51, MC100EL51
5VECL Differential Clock D
Flip‐Flop
Description
The MC10EL/100EL51 is a differential clock D flip-flop with reset.
The device is functionally similar to the E151 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E151 the EL51 is ideally
suited for those applications which require the ultimate in AC
performance.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EL51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input (pulled down to VEE) conditions.
The 100 Series contains temperature compensation.
Features
475 ps Propagation Delay
2.8 GHz Toggle Frequency
ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors on D, R, and CLK
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 73 devices
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KL51
ALYWG
G
SOIC8
D SUFFIX
CASE 751
1
8
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
KEL51
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
2M
M
G
14
4X
M
G
14
HL51
ALYWG
G
1
8
HEL51
ALYW
G
1
8
(Note: Microdot may be in either location)
H = MC10
K = MC100
4X = MC10
2M= MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = PbFree Package
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