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參數(shù)資料
| 型號(hào)： | MC100EP195FAR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | MC100EP195FAR2GOS |
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MC10EP195, MC100EP195
http://onsemi.com
16
MultiChannel Deskewing
The most practical application for EP195 is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a highspeed
system. To deskew multiple signal channels, each channel can
be sent through each EP195 as shown in Figure 8. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any highspeed system can be finetuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
EP195
IN
Q
IN
Q
#1
EP195
IN
Q
IN
Q
#2
EP195
IN
Q
IN
Q
#N
Digital
Data
Control
Logic
Figure 8. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP195s provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 9,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flipflop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31.
The programmed delay of the second EP195 is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP195 is too
long, the flipflop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flipflop output will be at a logic low. If the
programmed delay is correctly finetuned in the second
EP195, the flipflop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
EP195
IN
Q
IN
Q
#1
EP195
IN
Q
IN
Q
#2
Unknown Delay
Device
Control
Logic
D
CLK
Q
EP31
CLOCK
Figure 9. Multiple Channel Deskewing Diagram
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| MC100EP195MNG | 功能描述:延遲線/計(jì)時(shí)元素 BBG ECL PROG DELAY CHIP RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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