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參數(shù)資料
| 型號(hào)： | MC100EP196FAR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.36ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.36ns ~ 12.258ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC100EP196FAR2GOS |
MC100EP196
http://onsemi.com
12
Figure 4. AC Reference Measurement
IN
Q
tPHL
tPLH
VINPP = VIH(D) VIL(D)
VOUTPP = VOH(Q) VOL(Q)
Using the FTUNE Analog Input
The analog FTUNE pin on the EP196 device is intended
to add more delay in a tunable gate to enhance the 10 ps
resolution capabilities of the fully digital EP196. The level
of resolution obtained is dependent on the voltage applied to
the FTUNE pin.
To provide this further level of resolution, the FTUNE pin
must be capable of adjusting the additional delay finer than
the 10 ps digital resolution (See Logic Diagram). This
requirement is easily achieved because a 60 ps additional
delay can be obtained over the entire FTUNE voltage range
(See Figure 5). This extra analog range ensures that the
FTUNE pin will be capable even under worst case
conditions of covering a digital resolution. Typically, the
analog input will be driven by an external DAC to provide
a digital control with very fine analog output steps. The final
resolution of the device will be dependent on the width of the
DAC chosen.
To determine the voltage range necessary for the FTUNE
input, Figure 5 should be used. There are numerous voltage
ranges which can be used to cover a given delay range; users
are given the flexibility to determine which one best fits their
designs.
Figure 5. Typical EP196 Delay versus FTUNE Voltage
FTUNE VOLTAGE (V)
3.3 2.97 2.64 2.31 1.98 1.65 1.32 0.99 0.66 0.33
0
90
80
70
60
50
40
30
20
10
0
10
DELA
Y
(ps)
40°C
85°C
25°C
VCC = 0 V
VEE = 3.3 V
VCC
VEE
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