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參數(shù)資料
| 型號： | MC100EP221TB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 308K |
| 代理商： | MC100EP221TB |
6
MC100EP221
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
644
Table 6: PECL/ECL/HSTL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V,
VCC = VCCO = GND)
Symbol
Characteristics
TA = -40°C
TA = 25°C
TA = 85°C
Unit
Condition
y
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Clock input pair CLK0, CLK0, CLK1, CLK1b for PECL differential signals
VPP
Differential input voltagec
(peak-to-peak)
0.5
1.0
0.5
1.0
0.5
1.0
V
VCMR
Differential cross point
voltaged
CLK0
CLK1
1.0
0.3
VCC-0.4
VCC-1.3
1.0
0.3
VCC-0.4
VCC-1.3
1.0
0.3
VCC-0.4
VCC-1.3
V
fCLK
Input Frequency (PECL)
0
1.0
GHz
Clock input pair CLK0, CLK0, CLK1, CLK1 for ECL differential signals
VPP
Differential input voltage
(peak-to-peak)
0.5
1.0
0.5
1.0
0.5
1.0
V
VCMR
Differential cross point
voltage
CLK0
CLK1
VEE+1.0
VEE+0.3
-0.4
-1.3
VEE+1.0
VEE+0.3
-0.4
–1.3
VEE+1.0
VEE+0.3
-0.4
-1.3
V
fCLK
Input Frequency (ECL)
0
1.0
GHz
Clock input pair CLK1, CLK1 for HSTL differential signals
VDIF
Differential input voltagee
(peak-to-peak)
CLK1
0.4
1.0
0.5
1.0
0.5
1.0
V
VX
Differential cross point
voltagef
CLK1
0.68
0.9
0.68
0.9
0.68
0.9
V
fCLK
Input Frequency (HSTL)
0
1.0
GHz
PECL/ECL clock outputs (Q0-19, Q0-19)
tPD
Propagation Delay
CLK0 to Qx
CLK1 to Qx
350
370
460
500
600
640
390
440
520
570
660
710
480
530
630
680
750
800
ps
Diff.
VO(P-P)
Differential output voltage
(peak-to-peak) fO < 50 MHz
fO < 0.8 GHz
fO < 1.0 GHz
450
400
375
550
500
400
550
500
400
mV
tsk(O)
Output-to-output skew
(within device)
30
50
30
50
30
50
ps
Diff.
tsk(PP)
Output-to-output skew
(part-to-part)
270
ps
Diff.
tJIT(CC)
Output cycle-to-cycle jitter
(RMS)
TBD
ps
DCO
Output duty cycle
49.5
50
50.5
49.5
50
50.5
49.5
50
50.5
%
DCfref= 50%
tr, tf
Output Rise/Fall Time
100
500
100
500
100
500
ps
20% to 80%
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The difference between CLK0 and CLK1 is the
differential input threshold voltage (VCMR).
c. VPP (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
d. VCMR (AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay and part-to-
part skew.
e. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics. Only applicable to CLK1.
f.
VX (AC) is the crosspoint of the differential HSTL input signal. AC operation is obtained when the crosspoint is within the VX (AC) range
and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay and part-
to-part skew.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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