參數(shù)資料
型號: MC100EP446FAR2
廠商: ON Semiconductor
文件頁數(shù): 12/20頁
文件大?。?/td> 0K
描述: IC CONV 8BIT SER/PAR ECL 32LQFP
產(chǎn)品變化通告: LTB Notification 03/Jan/2008
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 數(shù)據(jù)管理
接口: 差分
電源電壓: 3 V ~ 5.5 V
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-LQFP(7x7)
包裝: 剪切帶 (CT)
安裝類型: 表面貼裝
其它名稱: MC100EP446FAROSCT
MC10EP446, MC100EP446
http://onsemi.com
2
25
26
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31
32
15
14
13
12
11
10
9
12345678
24
23
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18
17
16
Figure 1. LQFP32 Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
D0
D1
D3
D4
D7
VCC
SOUT
VEE
VBB2
V
CC
CKSEL
VEF
VEE
PCLK
D2
D5
D6
SOUT
VCF
SYNC
VCC
CLK
V
BB1
CKEN
V
EE
VCC
MC10EP446
MC100EP446
Figure 2. QFN32 Pinout (Top View)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
1
234
5
6
78
24
23
22
21
20
19
18
17
Exposed Pad (EP)
D0
D1
D3
D4
D7
V
CC
CKSEL
D2
D5
D6
CLK
V
BB1
CKEN
V
EE
SOUT
VEE
PCLK
SOUT
VCC
VEE
VBB2
VEF
VCF
SYNC
VCC
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0*D7*
ECL, CMOS, or TTL Parallel Data Input
SOUT, SOUT
ECL Differential Serial Data Output
CLK*, CLK*
ECL Differential Clock Input
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC*, SYNC**
ECL Conversion Synchronizing Differential Input (Reset)***
CKSEL*
ECL Clock Input Selector
CKEN*, CKEN*
ECL Clock Enable Differential Input
VCF
ECL, CMOS, or TTL Input Selector
VEF
ECL Reference Mode Connection
VBB1, VBB2
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
**Pins will default HIGH when left open.
***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK
initiates the conversion process synchronously on the next rising edge of CLK.
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