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參數(shù)資料
| 型號： | MC100EP809MNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:9 32-QFN |
| 標準包裝： | 74 |
| 系列： | 100EP |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數(shù)： | 2 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVDS，LVPECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 管件 |
MC100EP809
http://onsemi.com
6
Symbol
Characteristic
0°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOpp
Differential Output Voltage fout < 100 MHz
(Figure 4)
fout < 500 MHz
fout < 750 MHz
600
450
850
750
575
600
450
850
750
575
600
450
850
750
575
mV
tPLH
tPHL
Propagation Delay (Differential Configura-
tion)
LVPECL_CLK to Q
HSTL_CLK to Q
680
690
800
830
930
990
700
820
850
950
1000
780
790
920
950
1070
1110
ps
tskew
WithinDevice Skew (Note 6)
DevicetoDevice Skew (Note 7)
15
100
50
200
15
100
50
200
15
100
50
200
ps
tJITTER
Random Clock Jitter (Figure 4) (RMS)
1.4
3.0
1.4
3.0
1.4
3.0
ps
VPP
Input Swing (Differential Configuration)
LVPECL
HSTL
200
mV
tS
OE Set Up Time (Note 9)
0.5
ns
tH
OE Hold Time
0.5
ns
tr/tf
Output Rise/Fall Time
(20% 80%)
350
600
350
450
600
350
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to GND (Figure 7).
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. DevicetoDevice skew for identical transitions and conditions.
8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
9. OE Set Up Time is defined with respect to the rising edge of the clock. OE HightoLow transition ensures outputs remain disabled during
the next clock cycle. OE LowtoHigh transition enables normal operation of the next input clock (Figure 9).
0
100
200
300
400
500
600
700
800
900
0
100
200
300
400
500
600
700
800
900 1000
Figure 4. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
2
3
4
5
6
7
8
V
OPP
(mV)
t JITTER
ps
(RMS)
9
1
FREQUENCY (MHz)
VOPP
RMS JITTER
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