參數(shù)資料
型號: MC100EPT24MNR4G
廠商: ON SEMICONDUCTOR
元件分類: 電平轉換
英文描述: 3.3V LVTTL/LVCMOS to Differential LVECL Translator
中文描述: LVTTL/LVCMOS TO LVECL TRANSLATOR, COMPLEMENTARY OUTPUT, DSO8
封裝: LEAD FREE, DFN-8
文件頁數(shù): 4/8頁
文件大?。?/td> 135K
代理商: MC100EPT24MNR4G
MC100EPT24
http://onsemi.com
4
Table 6. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
=
3.0 V to
5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 4)
Symbol
Characteristic
40
°
C
25
°
C
85
°
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
max
Maximum Input Clock Frequency (Fig-
ure 2)
> 1
> 1
> 1
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential (Note 5)
300
500
800
300
530
800
300
560
800
ps
t
JITTER
t
r
t
f
RMS Random Clock Jitter (Figure 2)
0.2
< 1
0.2
< 1
0.2
< 1
ps
Output Rise/Fall Times
(20%
80%) @ 50 MHz
Q, Q
70
125
170
80
130
180
100
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 to GND
2.0 V.
5. Specifications for standard TTL input signal.
0
100
200
300
400
500
600
700
800
900
100
300
500
INPUT CLOCK FREQUENCY (MHz)
700
900
1100
1300
1
2
3
4
5
6
7
8
9
Figure 2. Output Voltage Amplitude (V
OUTpp
)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
éééééééééééééééééééééé
(JITTER)
O
R
éé
éé
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
Q
D
Q
D
Z
o
= 50
Z
o
= 50
50
50
V
TT
V
TT
= V
CC
2.0 V
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