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參數(shù)資料
| 型號(hào)： | MC100H681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Hex ECL/TTL Transceiver with Latches |
| 中文描述： | TTL TO ECL TRANSCEIVER, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 112K |
| 代理商： | MC100H681FN |
SEMICONDUCTOR TECHNICAL DATA
2–316
REV 2
Motorola, Inc. 1996
9/96
The MC10/100H681 is a dual supply Hex ECL/TTL transceiver with
latches in both directions. ECL controlled Direction and Chip Enable Bar
pins. There are two Latch Enable pins, one for each direction.
The ECL outputs are single ended and drive 50
. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads. The high driving ability of the TTL outputs make the device
ideal for bussing applications.
The ECL output levels are standard VOH and VOL cutoff equal to –2.0 V
(VTT). When the ECL ports are disabled the outputs go to the VOL cutoff
level. Multiple ECL VCCO pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
Separate Latch Enable Controls for each Direction
ECL Single Ended 50
I/O Port
High Drive TTL I/O Ports
Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
Dual Supply
Direction and Chip Enable Control Pins
Pinout: 28–Lead PLCC
(Top View)
1
5
6
7
8
9
10
11
25
24
23
22
21
20
19
26
27
28
2
3
4
12
13
14
15
16
17
18
TIO2
VT
GT
TIO1
VT
GT
TIO0
EIO5
VCCO
EIO4
VCCE
EIO3
VCCO
EIO2
T
V
G
T
V
G
T
D
L
E
C
L
E
V
Pin
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TI01
VT
GT
TI00
DIR
CEB
LEET
LETE
VEE
EI00
EI01
EI02
VCCO
EIO3
VCCE
EIO4
VCCO
EIO5
TI05
GT
G
VT
TI04
GT
VT
TIO3
TIO2
VT
GT
TTL I/O BIT 1
TTL VCC (5.0 V)
TTL GND (0 V)
TTL I/O Bit 0
Direction Control (ECL)
Chip Enable Bar Control (ECL)
bl ECL TTL C
Latch Enable ECL-TTL Control (ECL)
L t h E
bl TTL ECL C
Latch Enable TTL-ECL Control (ECL)
l ( 5 2/ 4 5 V)
ECL Supply (–5.2/–4.5 V)
ECL I/O BIT 0
ECL I/O BIT 1
ECL I/O BIT 2
ECL VCC(0 V) — Outputs
ECL VCC (0 V) — Outputs
TTL I/O BIT 3
ECL VCC (0 V)
ECL I/O BIT 4
ECL VCC (0 V) — Outputs
ECL I/O BIT 5
TTL I/O BIT 5
TTL G
(0
)
TTL VCC (5.0 V)
CC(
TTL I/O BIT 4
TTL GND (0 V)
(5 0 V)
TTL VCC (5.0 V)
TTL I/O BIT 3
TTL I/O BIT 2
TTL VCC(5 0 V)
TTL VCC (5.0 V)
TTL VCC(0 V)
TTL VCC (0 V)
t l (ECL)
0
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
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