參數(shù)資料
型號(hào): MC10110L
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Hex Schmitt-trigger Inverters 14-CDIP -55 to 125
中文描述: 10K SERIES, DUAL 3-INPUT OR GATE, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 1/4頁
文件大小: 76K
代理商: MC10110L
SEMICONDUCTOR TECHNICAL DATA
3–40
REV 6
Motorola, Inc. 1996
9/96
The MC10110 is designed to drive up to three transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines from a single point makes the
MC10110 particularly useful in clock distribution applications where minimum
clock skew is desired. Three VCC pins are provided and each one should be
used.
PD= 80 mW typ/pkg (No Load)
tpd= 2.4 ns typ (All Outputs Loaded)
tr, tf= 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1, 15
VCC2= PIN 16
VEE= PIN 8
12
13
14
11
10
9
2
3
4
7
6
5
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
相關(guān)PDF資料
PDF描述
MC10110P Hex Schmitt-trigger Inverters 14-CFP -55 to 125
MC10111L Replaced by SN54LS148 : 10-Line To 4-Line And 8-Line To 3-Line Priority Encoders 16-CDIP -55 to 125
MC10111 Dual 3-Input/3-Output NOR Gate
MC10111P Replaced by SN54LS148 : 10-Line To 4-Line And 8-Line To 3-Line Priority Encoders 16-CDIP -55 to 125
MC10113 Replaced by SN54LS148 : 10-Line To 4-Line And 8-Line To 3-Line Priority Encoders 16-CFP -55 to 125
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