參數(shù)資料
型號(hào): MC10113
廠商: ON SEMICONDUCTOR
英文描述: Data Selectors/Multiplexers 24-CDIP -55 to 125
中文描述: 四異或門
文件頁(yè)數(shù): 1/5頁(yè)
文件大小: 104K
代理商: MC10113
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
E
9
13
12
15
11
10
14
7
6
3
5
4
2
SEMICONDUCTOR TECHNICAL DATA
3–48
REV 5
Motorola, Inc. 1996
3/93
The MC10113 is a quad Exclusive OR gate, with an enable common to all
four gates. The outputs may be wire–ORed together to perform a 4–bit
comparison function (A = B). The enable is active low.
PD= 175 mW typ/pkg (No Load)
tpd= 2.5 ns typ
tr, tf= 2.0 ns typ (20% to 80%)
TRUTH TABLE
IN
E
OUTPUT
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
L
H
H
L
L
DIP
PIN ASSIGNMENT
VCC1
AOUT
BOUT
AIN
AIN
BIN
BIN
VEE
VCC2
DOUT
COUT
DIN
DIN
CIN
CIN
ENABLE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關(guān)PDF資料
PDF描述
MC10113FN Data Selectors/Multiplexers 24-CFP -55 to 125
MC10113L Data Selectors/Multiplexers 24-CFP -55 to 125
MC10113P Data Selectors/Multiplexers 24-CDIP -55 to 125
MC10115FN Quad Line Receiver
MC10115L Quad Line Receiver
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