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參數(shù)資料
| 型號(hào)： | MC10198FNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 諧振器 |
| 英文描述： | 10K SERIES, MONOSTABLE MULTIVIBRATOR, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | MC10198FNR2 |
MC10198
http://onsemi.com
2
DIP
PIN ASSIGNMENT
VCC1
Q
CEXT
EPOS
REXT
EXT.PULSE
WIDTH CONTROL
VEE
VCC2
HIGH-SPEED
INPUT
N/C
TRIGGER INPUT
N/C
ENEG
N/C
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
5
7
10
13
15
3
2
Q
64
VEE
VCC
CEXT
E pos
EXTERNAL PULSE
WIDTH CONTROL
ENEG
TRIGGER
INPUT
HI-SPEED
INPUT
TRUTH TABLE
EPos
ENeg
L
H
INPUT
OUTPUT
L
H
L
H
Triggers on both positive & negative input slopes
Triggers on positive input slope
Triggers on negative input slope
Trigger is disabled
REXT
1. At t = 0
a.) Apply VIHmax to Pin 5 and 10.
b.) Apply VILmin to Pin 15.
c.) Ground Pin 4.
2. At t
w 10 ns a.) Open Pin 1.
b.) Apply –3.0 Vdc to Pin 4.
Hold these conditions for
w10 ns.
3. Return Pin 4 to Ground and perform test as
indicated in Table 2.
Pins 1, 16 = VCC = Ground
Pins 6, 8 = VEE = –5.2 Vdc
Outputs loaded 50
to –2.0 Vdc
VIH max
VIL min
P1
-5.0
0
w 10 ns
t(ns)
-4.0
-3.0
-2.0
-1.0
0(Gnd)
10
20
Pin 1
open
30
TABLE 1 — PRECONDITION SEQUENCE
Pin
4
V
oltage
(Vdc)
w 10 ns
TABLE 2 — CONDITIONS FOR TESTING OUTPUT LEVELS
(See Table 1 for Precondition Sequence)
VILA max
VIL min
P2
VIHA max
VIL min
P3
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|---|---|
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