參數(shù)資料
型號(hào)： MC10210
廠商： Motorola, Inc.
英文描述： Dual 3-Input/3-Output OR Gate
中文描述： 雙3-Input/3-Output或門
文件頁(yè)數(shù)： 1/5頁(yè)
文件大小： 80K
代理商： MC10210
SEMICONDUCTOR TECHNICAL DATA
3–182
REV 5
Motorola, Inc. 1996
3/93
The MC10210 is designed to drive up to six transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR” –ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10210 particularly useful in clock distribution
applications where minimum clock skew is desired.
PD= 160 mW typ/pkg (No Loads)
tpd= 1.5 ns typ (All Output Loaded)
tr, tf= 1.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1, 15
VCC2= PIN 16
VEE= PIN 8
12
13
14
11
10
9
2
3
4
7
6
5
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
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