參數(shù)資料
型號： MC10212L
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CFP -55 to 125
中文描述： 10K SERIES, DUAL 3-INPUT OR/NOR GATE, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 1/5頁
文件大?。?/td> 103K
代理商： MC10212L
SEMICONDUCTOR TECHNICAL DATA
3–192
REV 5
Motorola, Inc. 1996
3/93
The MC10212 is designed to drive up to six transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10212 particularly useful in clock distribution
applications where minimum clock skew is desired.
PD= 160 mW typ/pkg (No Load)
tpd= 1.5 ns typ (All Outputs Loaded)
tr, tf= 1.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1, 15
VCC2= PIN 16
VEE= PIN 8
12
13
14
11
10
9
4
3
2
7
6
5
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
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