參數(shù)資料
型號: MC10E141FNG
廠商: ON Semiconductor
文件頁數(shù): 1/8頁
文件大小: 0K
描述: IC SHIFT REGISTR 8BIT ECL 28PLCC
產(chǎn)品變化通告: Dimensional change 21/Oct/2008
標(biāo)準(zhǔn)包裝: 37
系列: 10E
邏輯類型: 移位寄存器
輸出類型: 標(biāo)準(zhǔn)
元件數(shù): 1
每個元件的位元數(shù): 8
功能: 通用
電源電壓: 4.2 V ~ 5.7 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
其它名稱: MC10E141FNGOS
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 7
1
Publication Order Number:
MC10E141/D
MC10E141, MC100E141
5VECL 8-Bit Shift Register
Description
The MC10E/100E141 is an 8-bit full-function shift register. The
E141 performs serial/parallel in and serial/parallel out, shifting in
either direction. The eight inputs D0 D7 accept parallel input data,
while DL/DR accept serial input data for left/right shifting. The Qn
outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left
unterminated.
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the
Function Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
The 100 Series contains temperature compensation.
Features
700 MHz Min. Shift Frequency
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 565 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxE141FNG
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
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