VCC
參數(shù)資料
型號: MC10E196FN
廠商: ON Semiconductor
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC DELAY LINE 128TAP 28-PLCC
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標準包裝: 37
系列: 10E
標片/步級數(shù): 128
功能: 可編程
延遲到第一抽頭: 1.39ns
接頭增量: 20ps
可用的總延遲: 1.39ns ~ 3.63ns
獨立延遲數(shù): 1
電源電壓: 4.2 V ~ 5.7 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應商設備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
MC10E196, MC100E196
http://onsemi.com
2
D2
D3 D4 D5 D6 D7 NC
NC NC EN
SET
MIN
SET
MAX
CASCADE
FTUNE
NC
VCC
VCCO
Q
VCCO
D1
D0
LEN
VEE
IN
VBB
25
24
23
22
21
20
19
26
27
28
1
2
3
4
18
17
16
15
14
13
12
56
7
8
9
10
11
Figure 1. Pinout: PLCC28
(Top View)
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
* All VCC and VCCO pins are tied together on the die.
MC10E196
MC100E196
Table 1. PIN DESCRIPTION
PIN
FUNCTION
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
VBB
VCC, VCCO
VEE
NC
ECL Signal Input
ECL Input Enable (H Forces Q Low)
ECL MUX Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
ECL Linear Voltage Input
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. TRUTH TABLE
EN
L
Q = IN
EN
H
Q Logic Low
LEN
L
Pass Through D[0:10]
LEN
H
Latch D[0:10]
SETMIN
L
Normal Mode
SETMIN
H
Min Delay Path
SETMAX
L
Normal Mode
SETMAX
H
Max Delay Path
1
Figure 2. Logic Diagram Simplified
VBB
IN
EN
LEN
SET MIN
SET MAX
1
0
1
0
1
0
1
0
1
0
1
0
1
0
11
1
0
1
Q
CASCADE
7 BIT LATCH
LEN
Q
LATCH
D
4 GATES
8 GATES
16 GATES
* 1.25
* 1.5
D0
D1
D2
D3
D4
D5
D6
D7
* delays are 25% or 50% longer than
* standard (standard ≈ 80 ps)
LINEAR
RAMP
FTUNE
VEE
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