參數(shù)資料
型號(hào): MC10E196FNR2G
廠商: ON Semiconductor
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC DELAY LINE 128TAP 28-PLCC
產(chǎn)品變化通告: Dimensional change 21/Oct/2008
標(biāo)準(zhǔn)包裝: 500
系列: 10E
標(biāo)片/步級(jí)數(shù): 128
功能: 可編程
延遲到第一抽頭: 1.39ns
接頭增量: 20ps
可用的總延遲: 1.39ns ~ 3.63ns
獨(dú)立延遲數(shù): 1
電源電壓: 4.2 V ~ 5.7 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
MC10E196, MC100E196
http://onsemi.com
8
When the SET MAX pin of chip #1 is asserted the D0 and
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E196.
When cascading multiple PDC’s it will prove more cost
effective to use a single E196 for the Most Significant Bit
(MSB) of the chain while using E195 for the lower order
bits. This is due to the fact that only one fine tune input is
needed to further reduce the delay step resolution.
ADDRESS BUS (A0A6)
A7
INPUT
D1
D0
LEN
VEE
IN
VBB
D2
D3
D4
D5
D6
D7
EN
SET
MIN
SET
MAX
CASCADE
VCC
VCC0
Q
VCC0
D1
D0
LEN
VEE
IN
VBB
EN
SET
MIN
SET
MAX
CASCADE
VCC
VCC0
Q
VCC0
OUTPUT
D2
D3
D4
D5
D6
D7
E196
Chip #1
E196
Chip #2
Figure 3. Cascading Interconnect Architecture
FTUNE
LINEAR
INPUT
FTUNE
SET MIN
SET MAX
TO SELECT MULTIPLEXERS
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
D0
Q0
LEN
Reset Reset
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LEN
CASCADE
Figure 4. Expansion of the Latch Section of the E196 Block Diagram
Reset Reset
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