參數(shù)資料
型號(hào): MC10E197
廠商: ON SEMICONDUCTOR
英文描述: DATA SEPARATOR
中文描述: 數(shù)據(jù)分離器
文件頁數(shù): 10/16頁
文件大?。?/td> 217K
代理商: MC10E197
MC10E197
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–10
Calculations For a 2:7 Coding Scheme
Introduction
The circuit component values are calculated for a 2:7 coding
scheme employing a data rate of 23Mbit/sec. Since the
number of bits is doubled when the data is encoded, the data
clock is at half the frequency of the RDCLK signal. Thus, the
operating frequency for these calculations is 46MHz. Further,
the pole and zero positions are a function of the data rate;
hence, the component values derived by these calculations
must be scaled if a different operating frequency is used.
Finally, it should be noted that the values are optimized for
settling time.
The analysis is divided into three parts: static pole
positioning, dynamic pole positioning, and dynamic zero
positioning. Dynamic poles and zeros are those which the
designer may position, to yield the desired dynamic response,
through the judicious choice of element values. Static poles
are not directly controlled by the choice of component values.
Static Poles
Each op-amp introduces a pair of “static” complex
conjugate poles which must lie beyond the crossover
frequency. As obtained from the data sheets and laboratory
measurements, the two open loop poles for the MC34182D
are:
P*1a = – 0.1Hz
P*1b = –11.2Hz
Performing a root locus analysis and following the two
guidelines previously stated, an acceptable pole set is:
P1a = – 5.65 + j5.65MHz
P1b = – 5.65 – j5.65MHz
Both op-amps introduce a set of static complex conjugate
poles at these positions for a total of four poles. Further, the
loop gain for each op-amp associated with these pole
positions is determined from the root locus analysis to be:
A1 = A2 = 2.48 e15V
V
In addition to the op-amps, the integrator and the VCO each
contribute a static pole at the origin. Thus, there are a total of
six static poles.
Dynamic Poles
The filter input and the voltage divider sections each
contribute a dynamic pole. As stated previously, the filter input
pole should be positioned midway between the unity
crossover point and the phase detector sampling frequency.
Hence, the open loop filter input pole position is selected as:
P*1 = –1.24MHz
The voltage divider pole is set approximately one octave
higher than the filter input pole. Thus the open loop voltage
divider pole position is picked to be:
P*2 = – 2.57MHz
Dynamic Zero
Finally, the zero is positioned much less than one decade
before the crossover frequency; for this design the zero is
placed at:
z = – 311Hz
Once the dynamic pole and zero positions have been
determined, the phase margin is determined using a Bode
plot; if the phase margin is not sufficient, the dynamic poles
may be moved to improve the phase margin. Finally, a root
locus analysis is performed to obtain the optimum closed loop
pole positions for the dynamic characteristics of interest.
Component Values
Having determined the closed loop pole and zero positions
the component values are calculated. From the root locus
analysis the dynamic pole and zero positions are:
P1 = – 573kHz
P2 = – 3.06MHz
z = – 311Hz
Filter Input Subsection
Rearranging Equation 4:
CIN =
1
2
π
R1
p1
and substituting 573 kHz for the pole position and 1 k
for
the resistor value yields:
CIN = 278 pF
Augmenting Integrator Subsection
Rearranging Equation 6:
RA =
1
2
π
z
CA
and substituting 311Hz for the zero position and 0.1
μ
F for the
capacitor value yields:
RA = 5.11k
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