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| 型號： | MC10E445FNR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV 4BIT SER/PAR ECL 28-PLCC |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Aug/2008 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 10E |
| 類型： | 串行至并行/并行至串行轉(zhuǎn)換器 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MC10E445, MC100E445
http://onsemi.com
9
APPLICATIONS INFORMATION
The MC10E/100E445 is an integrated 1:4 serial to parallel
converter. The chip is designed to work with the E446 device
to provide both transmission and receiving of a high speed
serial data path. The E445, can convert up to a 2.0 Gb/s NRZ
data stream into 4-bit parallel data. The device also provides
a divide by four clock output to be used to synchronize the
parallel data with the rest of the system.
The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction with
the E446. Figure 5 illustrates the loop test architecture. The
architecture allows for the electrical testing of the link
without requiring actual transmission over the serial data
path medium. The SINA serial input of the E445 has an extra
buffer delay and thus should be used as the loop back serial
input.
SINB
SINA
SOUT
PARALLEL
DATA
PARALLEL
DATA
TO SERIAL
MEDIUM
FROM
SERIAL
MEDIUM
Figure 5. Loopback Test Architecture
The E445 features a differential serial output and a divide
by 8 clock output to facilitate the cascading of two devices
to build a 1:8 demultiplexer. Figure 6 illustrates the
architecture for a 1:8 demultiplexer using two E445’s; the
timing diagram for this configuration can be found on the
following page. Notice the serial outputs (SOUT) of the
lower order converter feed the serial inputs of the the higher
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock to
serial output propagation delay plus the setup time of the
serial input pins must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
TPD CLK to SOUT = 1150 ps and tS for SIN = 100 ps,
yields a minimum period of 1050 ps or a clock frequency of
950 MHz.
The clock frequency is significantly lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E445. By
delaying the clock feeding the second E445 relative to the
clock of the first E445 the frequency of operation can be
increased. The delay between the two clocks can be
increased until the minimum delay of clock to serial out
would potentially cause a serial bit to be swallowed
(Figure 7).
Q3
Q7
Q2
Q6
Q1
Q5
Q0
Q4
SIN
SOUT
E445a
Q3
Q2
Q1
Q0
SIN
E445b
CLOCK
SERIAL
INPUT
DATA
PARALLEL OUTPUT DATA
800 ps
1150 ps
100ps
CLOCK
Tpd CLK
to SOUT
Figure 6. Cascaded 1:8 Converter Architecture
With a minimum delay of 800 ps on this output the clock
for the lower order E445 cannot be delayed more than 800 ps
relative to the clock of the first E445 without potentially
missing a bit of information. Because the setup time on the
serial input pin is negative coincident excursions on the data
and clock inputs of the E445 will result in correct operation.
Figure 7. Cascade Frequency Limitation
800 ps
1150 ps
CLOCK B
Tpd CLK
to SOUT
CLOCK A
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock inputs
of the E445. By connecting the clock for the second E445 to
the complementary clock input pin the device will clock a
half a clock period after the first E445 (Figure 8). Utilizing
this simple technique will raise the potential conversion
frequency up to 1.4 GHz. The divide by eight clock of the
second E445 should be used to synchronize the parallel data
to the rest of the system as the parallel data of the two E445’s
will no longer be synchronized. This skew problem between
the outputs can be worked around as the parallel information
will be static for eight more clock pulses.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10E445FNR2G | 功能描述:計數(shù)器移位寄存器 5V ECL 4-Bit Serial to Parallell CNVRTR RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E446FN | 功能描述:計數(shù)器移位寄存器 5V ECL 4-Bit Serial RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E446FNG | 功能描述:計數(shù)器移位寄存器 5V ECL 4-Bit Serial to Parallell CNVRTR RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E446FNR2 | 功能描述:計數(shù)器移位寄存器 5V ECL 4-Bit Serial RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E446FNR2G | 功能描述:計數(shù)器移位寄存器 5V ECL 4-Bit Serial to Parallell CNVRTR RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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