參數(shù)資料
型號: MC10EP446FAR2
廠商: ON Semiconductor
文件頁數(shù): 6/20頁
文件大?。?/td> 0K
描述: IC CONV 8BIT SER/PAR ECL 32LQFP
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 2,000
接口: 差分
電源電壓: 3 V ~ 5.5 V
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-LQFP(7x7)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
其它名稱: MC10EP446FAR2OSTR
MC10EP446, MC100EP446
http://onsemi.com
14
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the
parallel input data after the a falling edge of SYNC
, followed by the falling edge CLK , on the next rising of edge of CLK
for CKSEL LOW
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
CLK
SYNC
SOUT
PCLK
D0
D02
D1
D2
D3
D4
D5
D6
D7
D22
D32
D42
D52
D62
D72
D03
D13
D23
D33
D43
D53
D63
D73
D12
CKSEL
D0
1
D1
1
D2
1
D3
1
D4
1
D5
1
D6
1
D7
1
D0
2
D1
2
D2
2
D3
2
D4
2
D6
2
D01
D21
D31
D41
D51
D61
D71
D11
D5
2
D04
D14
D24
D34
D44
D54
D64
D74
12
3
4
5
6
7
Data Latched
Figure 10. Synchronous Release of SYNC for CKSEL LOW
CLK
SYNC
(Asynchronous RESET)
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
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