參數(shù)資料
型號: MC10H145FN
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 16 x 4 Bit Register File(RAM)
中文描述: 16 X 4 STANDARD SRAM, 6 ns, PQCC20
封裝: PLASTIC, LCC-20
文件頁數(shù): 2/5頁
文件大?。?/td> 104K
代理商: MC10H145FN
MC10H145
MOTOROLA
MECL Data
DL122 — Rev 6
2–234
AC PARAMETERS
MC10H145
TA = 0 to +75
°
C,
VEE = –5.2 Vdc
±
5%
Characteristics
Symbol
Min
Max
Unit
Conditions
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
tACS
tRCS
tAA
0
0
0
4.0
4.0
6.0
ns
Measured from 50% of input to 50%
of output. See Note 2.
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
tW
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tWS
tWR
6.0
0
1.5
3.5
1.5
0
1.5
1.0
1.0
4.0
4.0
ns
tWSA = 3.5 ns
Measured at 50% of input to 50% of
output. tW = 6.0 ns.
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write Enable Setup Prior to Chip Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After Chip Select
Address Hold Time After Chip Select
Chip Select Minimum Pulse Width
tCSD
tCSW
tCSA
tCHD
tCHW
tCHA
tCS
tr, tf
0
0
0
1.0
0
2.0
4.0
ns
Guaranteed but not tested on
standard product. See Figure 1.
Rise and Fall Time
Address to Output
CS to Output
0.6
0.6
2.5
2.5
ns
Measured between 20% and 80%
points.
Capacitance
Input Capacitance
Output Capacitance
Cin
Cout
6.0
8.0
pF
Measured with a pulse technique.
NOTES: 1. Test circuit characteristics: RT = 50
, MC10H145. CL
capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL in a system environment, consult MECL System Design Handbook.
5.0 pF (including jig and Stray Capacitance). Delay should be derated 30 ps/pF for
FIGURE 1 — CHIP ENABLE STROBE MODE
A
DIN
WE
CS
TCSA
TCSW
TCSD
TCS
TCHA
TCHD
TCHW
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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