參數(shù)資料
型號: MC10H160
廠商: ON SEMICONDUCTOR
英文描述: Dual In/Single Out Autoswitching Power MUX, Auto Sw, Adj. Cur Limit, Adj. Vol Threshold, Sw Status 8-TSSOP -40 to 85
中文描述: 12位奇偶發(fā)生器檢查
文件頁數(shù): 1/3頁
文件大?。?/td> 95K
代理商: MC10H160
SEMICONDUCTOR TECHNICAL DATA
2–246
REV 5
Motorola, Inc. 1996
3/93
The MC10H160 is a 12–bit parity generator–checker. The output goes high
when an odd number of inputs are high providing the odd parity function.
Unconnected inputs are pulled to a logic low allowing parity detection and
generation for less than 12 bits. The MC10H160 is a functional pin duplication
of the standard 10K family part with 100% improvement in propagation delay
and no increase in power–supply current.
Propagation Delay, 2.5 ns Typical
Power Dissipation, 320 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current— Continuous
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
°
C
Storage Temperature Range— Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
88
78
88
mA
μ
A
Input Current High
Pins 3,5,7,10,12,14
Pins 4,6,9,11,13,15
391
457
246
285
246
285
Input Current Low
IinL
VOH
VOL
VIH
VIL
0.5
0.5
0.3
μ
A
Vdc
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
Propagation Delay
tpd
tr
tf
1.1
3.1
1.1
3.3
1.2
3.5
ns
Rise Time
0.55
1.5
0.55
1.6
0.75
1.7
ns
Fall Time
0.55
1.5
0.55
1.6
0.75
1.7
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
VCC1
OUT
IN1
IN2
IN3
IN4
IN5
VEE
VCC2
IN12
IN11
IN10
IN9
IN8
IN7
IN6
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
7
6
5
4
3
2
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
INPUT
Sum of
High Level
Inputs
OUTPUT
Pin 2
Even
Odd
Low
High
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關PDF資料
PDF描述
MC10H160FN 12-Bit Parity Generator-Checker
MC10H160L Autoswitching Power Mux 8-SON -40 to 85
MC10H160P Autoswitching Power Mux 8-TSSOP -40 to 85
MC10H160L 12-Bit Parity Generator-Checker
MC10H160P Autoswitching Power Mux 8-SON -40 to 85
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