參數(shù)資料
型號(hào): MC10H171FN
廠商: MOTOROLA INC
元件分類(lèi): 通用總線功能
英文描述: Dual Binary to 1-4 Decoder(Low)
中文描述: 10H SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PQCC20
封裝: PLASTIC, LCC-20
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 101K
代理商: MC10H171FN
SEMICONDUCTOR TECHNICAL DATA
2–9
REV 5
Motorola, Inc. 1996
3/93
The MC10H171 is a binary coded 2 line to dual 4 line decoder with selected
outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are
high. The common enable E, when high, forces all outputs high.
Propagation Delay, 2 ns Typical
Power Dissipation 325 mW Typical (same as MECL 10K)
Improved Noise Margin 150 mV (over operating voltage and
temperature range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current— Continuous
VEE
VI
Iout
–8 to 0
Vdc
0 to VEE
50
100
Vdc
— Surge
mA
Operating Temperature Range
TA
Tstg
0 to +75
°
C
°
C
Storage Temperature Range— Plastic
— Ceramic
–55 to +150
–55 to +165
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±
5%) (See Note)
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
IinH
IinL
VOH
VOL
VIH
VIL
85
77
85
mA
μ
A
μ
A
Vdc
Input Current High
425
265
265
Input Current Low
0.5
0.5
0.3
High Output Voltage
–1.02
–0.84
–0.98
–0.81
–0.92
–0.735
Low Output Voltage
–1.95
–1.63
–1.95
–1.63
–1.95
–1.60
Vdc
High Input Voltage
–1.17
–0.84
–1.13
–0.81
–1.07
–0.735
Vdc
Low Input Voltage
–1.95
–1.48
–1.95
–1.48
–1.95
–1.45
Vdc
AC PARAMETERS
0
°
25
°
75
°
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
Data
Select
tpd
0.5
0.5
2.0
2.6
0.5
0.5
2.1
2.7
0.5
0.5
2.2
2.8
ns
Rise Time
tr
tf
0.5
1.7
0.5
1.8
0.5
1.9
ns
Fall Time
0.5
1.7
0.5
1.8
0.5
1.9
ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
VCC1
E1
Q13
Q12
Q11
Q10
B
VEE
VCC2
E
E0
Q00
Q01
Q02
Q03
A
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
E0 14
A 9
B 7
E 15
E1 2
10 Q0 3
11 Q0 2
12 Q0 1
13 Q0 0
3 Q1 3
4 Q1 2
5 Q1 1
6 Q1 0
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
相關(guān)PDF資料
PDF描述
MC10H171P Dual Binary to 1-4 Decoder(Low)
MC10H173FN Quad 2-Input Multiplexer/Latch
MC10H173L Quad 2-Input Multiplexer/Latch
MC10H173P Quad 2-Input Multiplexer/Latch
MC10H173 QUAD 2-INPUT MULTIPLEXER / LATCH
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