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參數(shù)資料
| 型號： | MC1201A-P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Advanced Brushless Motor Control Chipset |
| 中文描述： | 先進的無刷電機控制芯片組 |
| 文件頁數(shù)： | 6/70頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MC1201A-P |
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6
Timing Interval
Command Byte Write Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
Host Cmd Hold Time
HostRdy Delay Time
~HostWrite Pulse Width
Write Data Setup Time
Write Data Hold Time
Data Word Read Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
HostCmd Hold Time
Read Data Access Time
Read Data Hold Time
~HostRead high to HI-Z Time
HostRdy Delay Time
Read Recovery Time
Data Word Write Timing
~HostSlct Hold Time
~HostSlct Setup Time
HostCmd Setup Time
HostCmd Hold Time
HostRdy Delay Time
~HostWrite Pulse Width
Write Data Setup Time
Write Data Hold Time
Write Recovery Time
DAC Interface Timing
I/OAddr Stable to ~I/OWrite setup time
~I/OWrite Pulse Width
Data Hold Time After ~I/OWrite
ClkOut Low to I/OAddr stable
ClkOut Low to ~I/OWrite Low
ClkOut Low to Data Valid
ClkOut Cycle Time
I/OAddr Stable to DACSlct High
~I/OWrite Low to DACSlct High
PWMOutput Timing
PWMOutput Frequency
T#
Mn.
Max.
Units
T6
T7
T8
T9
T13
T14
T15
T16
15
10
10
25
2000 (note 3)
nS
nS
nS
nS
nS
nS
nS
nS
70
50
35
30
T6
T7 (read only)
T8 (read only)
T9
T10
T11
T12
T13
T17
15
- 20
- 20
25
2000 (note 3)
nS
nS
nS
nS
nS
nS
nS
nS
nS
50
10
50
70
60
T6
T7
T8
T9
T13
T14
T15
T16
T18
15
10
10
25
2000 (note 3)
nS
nS
nS
nS
nS
nS
nS
nS
nS
70
50
35
30
60
T19
T20
T21
T22
T23
T24
T25
T26
T27
35
56
17
10
75
nS
nS
nS
nS
nS
nS
nS
nS
nS
95
40
92
92
160 typical (note 4)
66
44.5
24.5
Khz
note 1
note 2
~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met.
Chip-set performance figures and timng information valid at Fclk = 25.0 only. For timng information & performance parameters at Fclk <
25.0 Mhz, call PMD.
Two mcro seconds maximumto release interface before chip set responds to command
ClkOut fromCP is 1/4 frequency of ClkIn (CP chip).
note 3
note 4
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