參數(shù)資料
| 型號(hào)： | MC1241A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Advanced Brushless Motor Control Chipset |
| 中文描述： | 先進(jìn)的無刷電機(jī)控制芯片組 |
| 文件頁數(shù)： | 66/70頁 |
| 文件大小： | 474K |
| 代理商： | MC1241A |
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66
16-bit Parallel DAC Interface
The Interface between the MC1231A chip set and one or more 16 bit
DACs is shown in the following figure.
Comments on Schematic
The 16 Data bits and 2 address bits fromthe CP chip are latched in the
two 74FCT841 latches when the CP writes to address F hex, in the
address bits A0:A3. Three 74C373 latches could also be used. If this is
a write to the DAC, DACSLCT will be asserted during this CP bus cycle.
The assertion of DACSLCT will be latched by the fed-back and-or gate
and the next clock will set the DACWR flop. The second clock will set
the second shift flop which will clear the DACL latch. Since this latch
has been cleared the third clock will clear DACWR providing a two
clock DACWR level. The fourth clock will clear the second shift flop
returning the systemto its original state waiting for the next DACSLCT.
The DACWR assertion will enable the decoder causing the DAC
selected by the address bits stored in the transparent latch. The timng
described will produce a two clock write pulse to the DACs. This will be
about 320 nSec using I/OClk.
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