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參數(shù)資料
| 型號： | MC13109AFTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | MC13109AFTA |
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MC13109A
16
MOTOROLA RF/IF DEVICE DATA
Figure 7. Enable Timing Requirement
Clk
tsuEC
EN
50%
50%
50%
trec
Previous Data Latch
Last
Clock
First
Clock
50%
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 8 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 8. Microprocessor Interface Programming
Mode Diagrams
Data
8–Bit Address
EN
Data
EN
Address Register Programmng Mode
16–Bit Data
Data Register Programmng Mode
Latch
Latch
MSB
MSB
LSB
LSB
The MPU serial interface is fully operational within 100
μ
s
after the power supply has reached its minimum level during
power–up (See Figure 9). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx, and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Figure 9. Microprocessor Serial Interface
Power–Up Delay
VCC
tpuMPU
2.0 V
Data,
Clk, EN
Status Out
This is a digital output which indicates whether the latch
registers have been reset to their power–up default values.
Latch power–up default values are given in Figure 28. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the “Status Out”
pin will indicate this to the MPU so it can reload the correct
information into the latch registers.
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Status Latch Register Bits
á
Logic Level
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Status Out
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Latch bits at power–up default value
1
Data Registers
Figure 11 shows the data latch registers and addresses
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
“Don’t Care” bits can be loaded into the shift register first if
8–Bit bytes of data are loaded.
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