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參數(shù)資料
| 型號(hào)： | MC13158FTB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | WIDEBAND FM IF SUBSYSTEM FOR DECT AND DIGITAL APPLICATIONS |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP32 |
| 封裝： | PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 636K |
| 代理商： | MC13158FTB |
MC13158
18
MOTOROLA ANALOG IC DEVICE DATA
The internal resistance, Rint at the quadrature tank Pin 13
is approximately 13 k
and is considered in determining the
external resistance, Rext which is calculated from
((RT)(Rint)) (Rint – RT)
Rext
2110;
Rext
2.2 k
Rext
Thus, choose the standard value:
It is important to set the DC level of the detector output at
Pin 17 to center the peak to peak swing of the recovered
signal. In the equivalent internal circuit shown in the Pin
Function Description, the reference voltage at the positive
terminal of the inverting op amp buffer amplifier is set at
1.0 VBE. The detector DC level, V17 is determined by the
following equation:
V17
Thus, for a 1:1 ratio of R15/R17, V17 = 2.0 VBE = 1.4 Vdc.
Similarly for a 2:1, V17 = 1.5 VBE = 1.05 Vdc; and for 3:1,
V17 = 1.33 VBE = 0.93 Vdc.
Figure 19 shows the detector “S–Curves”, in which the
resistor ratio is varied while maintaining a constant gain (R17
is held at 62 k). R15 is 62 k for a 1:1 ratio; while R15 = 120 k
and 180 k to produce the 2:1 and 3:1 ratios. The IF signal into
the detector is swept
±
500 kHz about the 10.7 MHz IF center
frequency. The resulting curve show how the resistor ratio
and the supply voltage effects the symmetry of the “S–curve”
(Figure 21 Test Setup). For the 3:1 and 2:1 ratio, symmetry is
maintained with VS from 2.0 to 5.0 Vdc; however, for the 1:1
ratio, symmetry is lost at 2.0 Vdc
.
[((R15R17)
1) (R15R17)] VBE
Figure 19. Detector Output Voltage versus
Frequency Deviation
R15:R17 = 1:1
VS = 2.0 Vdc
– 600
2.5
D
FREQUENCY DEVIATION (kHz)
2.0
1.5
1.0
0.5
0
– 400
– 200
0
200
400
600
R15:R17 = 1:1
VS = 3.5 to 5.0 Vdc
R15:R17 = 2:1
VS = 2.0 to 5.0 Vdc
R15:R17 = 3:1
VS = 2.0 to 5.0 Vdc
1
fc = 10.7 MHz
R17 = 62 k
Test Setup – Figure 20
Figure 20. Demodulator “S–Curve” Test Setup
Wavetek Signal
Generator
Model 134
Oscilloscope
TEK 475
Signal Generator
Fluke 6082A
fc = 10.7 MHz
f =
±
500 kHz
MC13158
50
Output
Sweep Out
X Input
Y
Input
EXT
MOD In
DET
Out
RF Out
Lim In
Data Slicer Circuit
C20 at the input of the data slicer is chosen to maintain a
time constant long enough to hold the charge on the
capacitor for the longest strings of bits at the same polarity.
For a data rate at 576 kHz a bit stream of 15 bits at the same
polarity would equate to an apparent data rate of
approximately 77 kbps or 38 kHz. The time constant would
be approximately 26
μ
s. The following expression equates
the time constant, t, to the external components:
t
2
(R18)(C20)
Solve for C20:
C20
where the effective resistance R18 is a complex function of
the demodulator feedback resistance and the data slicer
input circuit. In the data input network the back to back diodes
form a charge and discharge path for the capacitor at Pin 20;
however, the diodes create a non–linear response. This
resistance is loaded by the , beta of the detector output
transistor; beta =100 is a typical value (see Figure 21). Thus,
the apparent value of the resistance at Pin 18 (DS IN1) is
approximately equal to:
t 2
(R18)
R18
R17100
where R17 is 82 k
, the feedback resistor from Pin 17 to 15.
Therefore, substituting for R18 and solving for C20:
C20
The closest standard value is 4.7 nF.
15.9 (t) R17
5.04 nF
Figure 21. Data Slicer Equivalent Input Circuit
VCC
R18
R17/
β
20
18
C20
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