SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, T" />
參數(shù)資料
型號: MC14012BDR2G
廠商: ON Semiconductor
文件頁數(shù): 4/8頁
文件大小: 0K
描述: IC GATE NAND DUAL P/N 14-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: 4000B
邏輯類型: 與非門
電路數(shù): 2
輸入數(shù): 4
電源電壓: 3 V ~ 18 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 8.8mA,8.8mA
邏輯電平 - 低: 1.5 V ~ 4 V
邏輯電平 - 高: 3.5 V ~ 11 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 100ns @ 15V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOICN
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: MC14012BDR2G-ND
MC14012BDR2GOSTR
MC14012B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise Time
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
tPLH, tPHL
5.0
10
15
160
65
50
300
130
100
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
14
CL
VSS
7
PULSE
GENERATOR
INPUT
OUTPUT
90%
50%
10%
50%
90%
20 ns
tPHL
tPLH
tTLH
tTHL
VOL
VOH
0 V
VDD
INPUT
OUTPUT
INVERTING
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
90%
50%
10%
VOL
VOH
OUTPUT
NONINVERTING
tTHL
tTLH
tPLH
tPHL
*
Figure 3. Switching Time Test Circuit and Waveforms
14
*
7
1, 13
VSS
VDD
*Inverter omitted
2, 9
3, 10
VDD
VSS
SAME AS
ABOVE
4, 11
5, 12
Figure 4. Circuit Schematic One of Two Gates Shown
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