Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 8
1
Publication Order Number:
MC14014B/D
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8bit static shift registers are
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a single monolithic structure. These shift registers find primary
use in paralleltoserial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.
Features
Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
“Q” Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
MC14014B PinforPin Replacement for CD4014B
MC14021B PinforPin Replacement for CD4021B
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
140xxBG
AWLYWW
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Indicator
See detailed ordering and shipping information in the package
dimensions section on page
6 of this data sheet.
ORDERING INFORMATION
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