MC14022B
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5
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
VSS
VDD
VSS
A
B
S1
Cout
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLOCK
ENABLE
RESET
Vout
ID
EXTERNAL
POWER
SUPPLY
Output
Sink Drive
Output
Source Drive
Outputs
Clock to desired
Output
(S1 to B)
(S1 to A)
Carry
Clock to Q5
thru Q7
(S1 to B)
S1 to A
VGS =
VDD
VDD
VDS =Vout VDD
Vout
Figure 2. Typical Power Dissipation Test Circuit
VDD
VSS
Cout
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLOCK
ENABLE
RESET
ID
PULSE
GENERATOR
500
mF
0.01
mF
CERAMIC
fc
CL
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 3. Counter Expansion
R
C
CE
MC14022B
Q0 Q1
Q6 Q7
7 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
R
C
CE
MC14022B
Q0 Q1
Q6 Q7
R
C
CE
MC14022B
Q1
Q6 Q7
6 DECODED
OUTPUTS
6 DECODED
OUTPUTS