SWITCHING CHARACTERISTICS (Note 5) (CL
參數(shù)資料
型號: MC14022BDR2G
廠商: ON Semiconductor
文件頁數(shù): 4/8頁
文件大小: 0K
描述: IC COUNTER OCTAL 4STAGE 16-SOIC
標準包裝: 1
系列: 4000B
邏輯類型: 二進制計數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 8
復位: 異步
計數(shù)速率: 16MHz
觸發(fā)器類型: 正,負
電源電壓: 3 V ~ 18 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC
包裝: 剪切帶 (CT)
其它名稱: MC14022BDR2GOSCT
MC14022B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Reset to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
5.0
10
15
500
230
175
1000
460
350
ns
Propagation Delay Time
Clock to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
tPLH,
tPHL
5.0
10
15
400
175
125
800
350
250
ns
Propagation Delay Time
Clock to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
5.0
10
15
275
125
95
1000
460
350
ns
TurnOff Delay Time
Reset to Cout
tPLH = (1.7 ns/pF) CL + 315 ns
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH = (0.5 ns/pF) CL + 100 ns
tPLH
5.0
10
15
400
175
125
800
350
250
ns
Clock Pulse Width
tWH
5.0
10
15
250
100
75
125
50
35
ns
Clock Frequency
fcl
5.0
10
15
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tWH
5.0
10
15
500
250
190
250
125
95
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
ns
Clock Input Rise and Fall Time
tTLH, tTHL
5.0
10
15
No Limit
Clock Enable Setup Time
tsu
5.0
10
15
350
150
115
175
75
52
ns
Clock Enable Removal Time
trem
5.0
10
15
420
200
140
260
100
70
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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