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參數(shù)資料
型號: MC14023BFEL
廠商: ON Semiconductor
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC GATE NAND TRPL 3INP 14SOEIAJ
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標準包裝: 2,000
系列: 4000B
邏輯類型: 與非門
電路數(shù): 3
輸入數(shù): 3
電源電壓: 3 V ~ 18 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 8.8mA,8.8mA
邏輯電平 - 低: 1.5 V ~ 4 V
邏輯電平 - 高: 3.5 V ~ 11 V
額定電壓和最大 CL 時的最大傳播延遲: 100ns @ 15V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應商設備封裝: SOEIAJ-14
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
MC14001B Series
http://onsemi.com
7
TYPICAL BSERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
Figure 10. VDD = 15 Vdc
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
12
14
16
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
Vout
VO
VIL
0
VIH
Vin
VDD
Vout
VO
VIL
0
VIH
Vin
VDD
(a) Inverting Function
(b) NonInverting Function
VSS = 0 VOLTS DC
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