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參數(shù)資料
| 型號(hào)： | MC14025BFELG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE NOR TRPL 3INPUT 14SOEIAJ |
| 產(chǎn)品變化通告： | Product Discontinuation 30/Sept/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 4000B |
| 邏輯類型： | 或非門 |
| 電路數(shù)： | 3 |
| 輸入數(shù)： | 3 |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 8.8mA，8.8mA |
| 邏輯電平 - 低： | 1.5 V ~ 4 V |
| 邏輯電平 - 高： | 3.5 V ~ 11 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 100ns @ 15V，50pF |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | SOEIAJ-14 |
| 封裝/外殼： | 14-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
MC14001B Series
http://onsemi.com
4
BSERIES GATE SWITCHING TIMES
Characteristic
Symbol
VDD
Vdc
Min
Typ (6)
Max
Unit
Output Rise Time, All BSeries Gates
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time, All BSeries Gates
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
8Input Gates (MC14068B, MC14078B)
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns
tPLH, tPHL
5.0
10
15
5.0
10
15
5.0
10
15
125
50
40
160
65
50
200
80
60
250
100
80
300
130
100
350
150
110
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
14
CL
VSS
7
PULSE
GENERATOR
INPUT
OUTPUT
90%
50%
10%
50%
90%
20 ns
tPHL
tPLH
tTLH
tTHL
VOL
VOH
0 V
VDD
INPUT
OUTPUT
INVERTING
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
90%
50%
10%
VOL
VOH
OUTPUT
NON-INVERTING
tTHL
tTLH
tPLH
tPHL
*
Figure 1. Switching Time Test Circuit and Waveforms
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