參數(shù)資料
型號(hào): MC14027BCPG
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 0K
描述: IC FLIP-FLOP JK DUAL CMOS 16DIP
標(biāo)準(zhǔn)包裝: 500
系列: 4000B
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: JK 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 13MHz
延遲時(shí)間 - 傳輸: 50ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 8.8mA,8.8mA
電源電壓: 3 V ~ 18 V
工作溫度: -55°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1124 (CN2011-ZH PDF)
其它名稱: MC14027BCPGOS
Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 7
1
Publication Order Number:
MC14027B/D
MC14027B
Dual J-K Flip-Flop
The MC14027B dual JK flipflop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flipflop. These devices may be
used in control, register, or toggle functions.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic EdgeClocked FlipFlop Design
Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
PositiveGoing Edge of the Clock Pulse
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4027B
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14027BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
14027BG
AWLYWW
A
= Assembly Location
WL
= Wafer Lot
YY, Y
= Year
WW
= Work Week
G
= PbFree Indicator
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
16
1
16
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