SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, T" />
參數(shù)資料
型號(hào): MC14040BDR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 0K
描述: IC COUNTER 12BIT CMOS 16SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 4000B
邏輯類(lèi)型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 12
計(jì)數(shù)速率: 10MHz
觸發(fā)器類(lèi)型: 負(fù)邊沿
電源電壓: 3 V ~ 18 V
工作溫度: -55°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): MC14040BDR2OSDKR
MC14040B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise and Fall Time
TTLH, TTHL = (1.5 ns/pF) CL + 25 ns
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns
TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
tPHL, tPLH = (0.5 ns/pF) CL + 95 ns
Clock to Q12
tPHL, tPLH = (1.7 ns/pF) CL + 2415 ns
tPHL, tPLH = (0.66 ns/pF) CL + 867 ns
tPHL, tPLH = (0.5 ns/pF) CL + 475 ns
tPLH,
tPHL
5.0
10
15
260
115
80
520
230
160
ns
5.0
10
15
1625
720
500
3250
1440
1000
ns
Propagation Delay Time
Reset to Qn
tPHL = (1.7 ns/pF) CL + 485 ns
tPHL = (0.86 ns/pF) CL + 182 ns
tPHL = (0.5 ns/pF) CL + 145 ns
tPHL
5.0
10
15
370
155
115
740
310
230
ns
Clock Pulse Width
tWH
5.0
10
15
385
150
115
140
55
38
ns
Clock Pulse Frequency
fcl
5.0
10
15
2.1
7.0
10.0
1.5
3.5
4.5
MHz
Clock Rise and Fall Time
tTLH, tTHL
5.0
10
15
No Limit
ns
Reset Pulse Width
tWH
5.0
10
15
960
360
270
320
120
80
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
PULSE
GENERATOR
500
mF
0.01
mF
CERAMIC
VDD
VSS
CL
ID
Q1
Q2
Qn
C
R
20 ns
VDD
VSS
90%
50%
10%
CLOCK
50% DUTY CYCLE
VDD
VSS
CL
Q1
Q2
Qn
C
R
20 ns
CLOCK
90%
50%
10%
tWH
tPHL
tPLH
Q
90%
50%
10%
tTLH
tTHL
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