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參數(shù)資料
| 型號： | MC14046BDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Phase Locked Loop |
| 中文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 253K |
| 代理商： | MC14046BDW |
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14046B
The MC14046B phase locked loop contains two phase comparators, a
voltage–controlled oscillator (VCO), source follower, and zener diode. The
comparators have two common signal inputs, PCAin and PCBin. Input PCAin
can be used directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. The self–bias circuit
adjusts small voltage signals in the linear region of the amplifier. Phase
comparator 1 (an exclusive OR gate) provides a digital error signal PC1out,
and maintains 90
°
phase shift at the center frequency between PCAin and
PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2out and LD, and
maintains a 0
°
phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout whose
frequency is determined by the voltage of input VCOin and the capacitor and
resistors connected to pins C1A, C1B, R1, and R2. The source–follower
output SFout with an external resistor is used where the VCOin signal is
needed but no loading can be tolerated. The inhibit input Inh, when high,
disables the VCO and source follower to minimize standby power
consumption. The zener diode can be used to assist in power supply
regulation.
Applications include FM and FSK modulation and demodulation, fre-
quency synthesis and multiplication, frequency discrimination, tone decod-
ing, data synchronization and conditioning, voltage–to–frequency
conversion and motor speed control.
Buffered Outputs Compatible with MHTL and Low–Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin–for–Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited
Phase Comparator 2 switches on Rising Edges and is not Duty Cycle
Limited
BLOCK DIAGRAM
PCAin
PCBin
VCOin
INH
14
3
9
5
VDD = PIN 16
VSS = PIN 8
2
PC1out
13 PC2out
1
LD
4
VCOout
11 R1
12 R2
6
C1A
7
C1B
10 SFout
15 ZENER
VSS
SELF BIAS
CIRCUIT
PHASE
COMPARATOR 1
PHASE
COMPARATOR 2
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
SOURCE FOLLOWER
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
R2
PC2out
PCAin
ZENER
VDD
VCOin
SFout
R1
VCOout
PCBin
PC1out
LD
VSS
C1B
C1A
INH
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參數(shù)描述 |
|---|---|
| MC14046BDWG | 功能描述:鎖相環(huán) - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC14046BDWR2 | 功能描述:鎖相環(huán) - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC14046BDWR2G | 功能描述:鎖相環(huán) - PLL LOG CMOS PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC14046BF | 功能描述:鎖相環(huán) - PLL LOG CMOS PHASE RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC14046BFEL | 功能描述:鎖相環(huán) - PLL LOG CMOS PHASE RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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