參數(shù)資料
型號(hào): MC14070BCL
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: CMOS SSI Quad Exclusive OR and NOR Gates
中文描述: 4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, CDIP14
封裝: CERAMIC, DIP-14
文件頁數(shù): 2/4頁
文件大小: 176K
代理商: MC14070BCL
MOTOROLA CMOS LOGIC DATA
MC14070B MC14077B
2
VDD
10
0.05
0.05
0.05
“1” Level
VOH
5.0
15
14.95
4.95
14.95
5.0
15
0
14.95
Vdc
Input Voltage
(VO = 13.5 or 1.5 Vdc)
4.95
15
4.0
6.75
4.0
4.95
4.0
Vdc
(VO = 1.5 or 13.5 Vdc)
“0” Level
“1” Level
15
11
11
8.25
Vdc
Output Drive Current
(VOH = 9.5 Vdc)
7.0
10
– 1.3
– 2.25
7.0
11
mAdc
(VOL = 1.5 Vdc)
– 1.6
15
4.2
3.4
8.8
– 0.9
Input Current
Iin
Cin
15
±
0.1
±
0.00001
±
0.1
2.4
±
1.0
μ
Adc
Input Capacitance
5.0
7.5
pF
15
1.0
0.0015
1.0
30
Total Supply Current**
(CL = 50 pF on all outputs, all
IT
IT = (0.3
μ
A/kHz) f + IDD
5.0
μ
Adc
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
(CL = 50 pF)
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
μ
H (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
tPHL
5.0
100
200
15
55
110
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
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