參數(shù)資料
型號(hào): MC14077BD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: IEEE 802.3af PoE Powered Device Controllers 8-TSSOP -40 to 85
中文描述: 4000/14000/40000 SERIES, QUAD 2-INPUT XNOR GATE, PDSO14
封裝: PLASTIC, SOIC-14
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 176K
代理商: MC14077BD
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14070B MC14077B
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
per Pin
* Maximum Ratings are those values beyond which damage to the device may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
Vin
CL
*
IDD
20 ns
20 ns
VDD
VSS
90%
50%
10%
Vin
1/f
50% DUTY CYCLE
* Inverted output on MC14077B only.
Figure 2. Switching Time Test Circuit and Waveforms
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
IN 2C
OUTD
IN 1D
IN 2D
VDD
IN 1C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B
VDD
CL
20 ns
VSS
VSS
90%
50%
10%
OUTPUT
#
*
20 ns
VOH
VOL
VDD
tTHL
tTLH
90%
50%
10%
tPLH
tPHL
INPUT
* Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
PULSE
GENERATOR
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
MC14070B
QUAD Exclusive OR
Gate
MC14077B
QUAD Exclusive NOR
Gate
13
11
12
9
8
6
5
2
1
10
4
3
13
12
9
8
6
5
2
1
11
10
4
3
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
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