參數(shù)資料
型號: MC14093BD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input NAND Schmitt Trigger
中文描述: 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: PLASTIC, SOIC-14
文件頁數(shù): 1/6頁
文件大?。?/td> 223K
代理商: MC14093BD
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14093B
) %&)( *
"$#(( '#!! '
The MC14093B Schmitt trigger is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the
MC14011B quad 2–input NAND gate for enhanced noise immunity or to
“square up” slowly changing waveforms.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Compatible with CD4093
Can be Used to Replace MC14011B
per Pin
PD
* Maximum Ratings are those values beyond which damage to the device may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
EQUIVALENT CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
+ !
+
!
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
LOGIC DIAGRAM
13
11
VDD = PIN 14
VSS = PIN 7
10
4
3
12
9
8
6
5
2
1
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